1. Field
This disclosure relates generally to a processor system and, more specifically to techniques for cache injection in a processor system responsive to a specific instruction sequence.
2. Related Art
Disparity between processor and memory speeds (also referred to as “the memory wall”) may adversely affect application performance. For example, applications that perform scientific and vector computation, encryption, signal processing, string processing, image processing, and deoxyribonucleic acid (DNA) sequence matching may be adversely affected by the memory wall. A number of different techniques (e.g., data caching, prefetching, software access ordering, and hardware-assisted access ordering) have been employed in an attempt to improve application performance. While the afore-mentioned techniques have generally proven effective for a variety of workloads, memory latency and memory traffic delays may still be encountered when accessing input/output (I/O) data (e.g., network messages).
To reduce delays associated with accessing I/O data, a number of cache injection policies have been proposed. In general, cache injection policies move I/O data into a cache before the I/O data is accessed in an attempt to minimize cache-miss latency. Information on which a cache injection policy is based may reside in various locations. For example, cache injection policy information may reside at a network interface controller (NIC), an I/O bridge, or at a cache. As one example, a NIC with access to operating system (OS) scheduling information may select a cache in which to inject I/O data based on which processor is scheduled to execute a thread that will consume the I/O data. As another example, a cache may include hardware support for storage of a list of addresses an application is expected to utilize in a selected number of subsequent processor cycles. The cache may then snoop addresses associated with data on a bus and store the data in the cache when the address on the bus is present in the list of addresses.